Search - verilog ip

[VHDL-FPGA-Verilog] SDR_SDRAM_IP

Description: SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
Platform: | Size: 2360320 | Author: peteryu010 | Hits:

[VHDL-FPGA-Verilog] 1_02_FullAdd4

Description: 四位元全加器,為Verilog/VHDL構成的IP模組電路-4bit fulladder
Platform: | Size: 12288 | Author: ytkao | Hits:

[VHDL-FPGA-Verilog] dma_0

Description: SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
Platform: | Size: 5120 | Author: zy | Hits:

[VHDL-FPGA-Verilog] FIFOED_UART

Description: CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
Platform: | Size: 6144 | Author: 杨胜尧 | Hits:

[VHDL-FPGA-Verilog] i2c.tar

Description: I2C verilog IP, can be synthesized and fpga proven.
Platform: | Size: 699392 | Author: Jason | Hits:

[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

Description: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Platform: | Size: 33792 | Author: 张秋光 | Hits:

[TCP/IP stack] MAC_verilog

Description: 以太网MAC网卡的Verilog源代码，可以节省TCP/IP协议的设计开发时间。-Verilog source code for Ethernet MAC network card, you can save the TCP/IP protocol design and development time.
Platform: | Size: 125952 | Author: lxk | Hits:

[Windows Develop] EEthhernet_vet

Description: Ethernet(以太网)verilog ip core用veriloggHDL语言写的以太网软核，对学习verilog语言与以太网有非常大帮助。 -Ethernet (Ethernet) Verilog the ip core with veriloggHDL language Ethernet soft-core, there is a very big help to learn verilog language and Ethernet.
Platform: | Size: 907264 | Author: 面积 | Hits:

[Software Engineering] VERILOGUSB2.0-IP

Description: USB IP核 verilog 语言完整的use ip核-use ip verilog HDL
Platform: | Size: 588800 | Author: 赵彦选 | Hits:

[VHDL-FPGA-Verilog] IP-coreincluding-VHDL-and-Verilog

Description: 芯片设计必须解剖的IP核（包含VHDL和Verilog代码）-The IP core chip design must anatomy (including VHDL and Verilog code)
Platform: | Size: 1180672 | Author: 张磊 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
Platform: | Size: 74752 | Author: shen jun | Hits:

[VHDL-FPGA-Verilog] Altera-SDRAM_controller-IP-CORE

Description: ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
Platform: | Size: 2378752 | Author: mr jiang | Hits:

[VHDL-FPGA-Verilog] ARM-Verilog-HDL-IP-CORE

Description: ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
Platform: | Size: 48128 | Author: xuyanwu | Hits:

[Other] sdr-sdram-verilog

Description: SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
Platform: | Size: 1277952 | Author: wushj | Hits:

[VHDL-FPGA-Verilog] HY57V64_control

Description: 本代码用verilog而不是直接在nios中用ip核来实现HY57V641620FTP-6的读写，时序完全正确，从串口输出来验证的数据完全正确。附带说明和参考资料。希望对您有帮助。-This code is used instead of directly in verilog ip core nios used to achieve HY57V641620FTP-6 reading and writing, the timing exactly right, from the serial data output to verify entirely correct. With notes and references. I hope for your help.
Platform: | Size: 15746048 | Author: 普尔 | Hits:

[Compress-Decompress algrithms] fpga-jpeg-Verilog

Description: jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
Platform: | Size: 109568 | Author: wanghaiwei | Hits:

[VHDL-FPGA-Verilog] Cyclone4_SD_Card_Audio_Player

Description: 基于cyclone4 FPGA芯片的音频播放器完成项目工程，包括SOPC项目代码，以及SD卡读取模块Verilog IP，以及完整的Q2下项目工程。-Cyclone4 FPGA chip based audio player to complete the project works, including the SOPC project code, and SD card reader module IP, as well as complete Q2 next project.
Platform: | Size: 2372608 | Author: bankfly | Hits:

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